Effects of space radiation on electronic devices

Space radiation is a mixture of charged particles moves with high velocities. Because the particles are charged, then when they hit semiconductor they influence on its electrical characteristics and cause effects which may lead to failure.

Accumulative effects

When an electronic device is a long term exposure to space radiation, then charged particles make on it permanently and irreparable damages which finally results in its failure. The device resistance on long term exposition of space radiation is one of the most important factors, which decide about the possible lifetime of a spacecraft.

Total Ionization Dose (TID)

When high-energy level partition traverse a semiconductor, then electron and hole pairs are produced. External electric field moves electrons and holes in opposite directions along the direction of the field. Electrons very quickly leave the semiconductor, but holes accumulate inside it (gate-oxide hole capture phenomenon).

Schematic  of  n-channel  MOSFET  illustrating  radiation-induced  charging  of the gate oxide
Schematic of n-channel MOSFET illustrating radiation-induced charging of the gate oxide

The extra electric field produced by accumulated charge has an impact on transistors properties like threshold voltage, transmission delays, static current and amplification coefficient. At some level of the damages, the component fails.

TID is measurable and is given as an amount of ionization energy deposited in the matter of component with rad unit 1rad = 0.01 J/kg. Different technology can withstand different levels of TID, eg. typical CMOS is in a range from 1 to 10 [krad], but rad hardened devices are in the range from 100[krad]-1[Mrad], bipolar technology is in the range 10-100[krad].

Displacement Damage Effect

The electric charge accumulated in the component is relevant to TID, whereas displacement damage effect is caused by mechanical energy acquired by the component’s crystal lattice when high-energy level particle arrives at it. If the energy of the incoming particle is sufficiently large, then it will displace the atoms within lattice to form a defect cluster. The defect influences on the component characteristic. The set of types of possible affected components is narrower than for TID, and they are bipolar transistors, solar panels and photoelectric devices. As a result of the damage, efficiency of solar panels is decreased, bipolar transistors have changed amplification coefficient, CCD cameras suffer for artefacts on captured images.

Transient effects

When heavy-ion pass through the active volume of electronic device it deposes a charge along its trace and this charge is collected by the electric field of the device. These probabilistic events cause associated “iono-current”, which can induce several effects.

Single Event Latch-up (SEL)

The problem is with CMOS component structure, which is not ideal and contains parasitic PNPN structures which can be presented as an equivalent of system of two connected transistors. In some circumstances, when charged particles will hit the silicon, both parasitic transistors are switched on and electric short occurs which cause high current. As a result of the event whole component may be destroyed because it becomes over-current and overheated. To prevent dramatic consequences of SEL the device must be equipped with security components which detects over-current and cuts off power supply. An SEL may or may not cause permanent device damage, but latent damage concern must be addressed for all SEL sensitive devices.

The picture of PNPN structure and its parasetic structure
PNPN component: (a) NOT gate. (b) Equivalent circuit./Fault-Tolerance Techniques for Spacecraft Control Computers

Single Event Upset (SEU)

The main effect of SEU is an unintentional change of the component state when the component was hit by a hi-energetic particle ( heavy-ion or proton). SEU is not so destructive like SEL, and its effects are in most(!) cases revertible. This may occur in digital, analogue, and optical components or may have effects in surrounding interface circuitry.

Bit flip

Memories are vulnerable to SEU. When an effect is a change in one bit of byte, then we named it SEU, if multiple bits are flipped, then the effect is named MBU – multiple bits upset. Bit flips are usually reversible by rewriting affected memory, but sometimes the damage is persistent – very small MOS transistors may be set by a single particle in the fixed state forever, the effect is named Single Event Hard (SEH) or stuck bit failure.

Picture of SEU on SRAM cell
Simplified example of bit flip of SRAM cell, charge of particle change state of the component in A and B points/Fault-Tolerance Techniques for Spacecraft Control Computers

Single Event Functional Interrupt (SEFI)

SEFI event is revertible and happens when a particle hits control or configuration element of the device, for example, address register of CPU, a configuration of FPGA, control element of memory, as result whole device resets, lock-up, or fail in another detectable way, but does not requires power cycling of the device (off and back on) to restore its operability (unlike SEL)

Single Event Transient (SET)

When high level energetic particle will hit electronic circuit, then it may generate inside the circuit peak of voltage, which can disturb work of the component. If the effect affect a logical component then it may generate SEU, but when it affects linear elements, then it may generate temporary interference which can disturb work of analog parts of the system. SET is a temporary effect, after some time harmful peak of voltage disappears and system is no longer disturbed with it.

Damage to power components

MOSFET power transistor consists thousands of connected MOS transistors with a large contact area between the source and the drain, what creates parasitic NPN BJT transistor structure.

Single Event Burnout (SEB)

When a MOSFET is turned off, the source has a high voltage. The penetration of high‐energy level particles through this high voltage source zone results in the activation of the parasitic transistor and in consequences high current between its emitter and collector what breaks down the MOSFET.
BJT. A High voltage is a necessary condition for SEB. Power MOSFETs, BJTs, and logic MOS transistors operating at low voltages will not experience SEB failure.

Picture of MOSFET parasitic BJT structure that leads to SEB effects
MOSFET parasitic BJT structure that leads to SEB/Fault-Tolerance Techniques for Spacecraft Control Computers

Single Event Gate Rapture (SEGR)

Bombardment by heavy ions to the lower part of the gate will produce high-density plasma in the vicinity of the ion’s track within the substrate. The electric field results in the electron‐hole pair drifting in the opposite direction to accumulate charge and when the voltage between the two opposite ends of a gate‐oxide structure is sufficiently high, it will irreversible break down the transistor.

Picture presents SEGR effects
SEGR mechanism/Fault-Tolerance Techniques for Spacecraft Control Computers